The present invention relates generally to semiconductor device manufacturing, and, more particularly, to a method and system for verification of resolution enhancement techniques and optical proximity correction in lithography.
The fabrication of integrated circuits on a semiconductor substrate typically includes multiple photolithography steps. A photolithography process begins by applying a thin layer of a photoresist material to the substrate surface. The photoresist is then exposed through a photolithography exposure tool to a radiation source that changes the solubility of the photoresist at areas exposed to the radiation. The photolithography exposure tool typically includes transparent regions that do not interact with the exposing radiation and a patterned material or materials that do interact with the exposing radiation, either to block it or to shift its phase.
As each successive generation of integrated circuits crowds more circuit elements onto the semiconductor substrate, it becomes necessary to reduce the size of the features, i.e., the lines and spaces that make up the circuit elements. The minimum feature size that can be accurately produced on a substrate is limited by the ability of the fabrication process to form an undistorted optical image of the mask pattern onto the substrate, by the chemical and physical interaction of the photoresist with the developer, and by the uniformity of the subsequent process (e.g., etching or diffusion) that uses the patterned photoresist.
When a photolithography system attempts to print circuit elements having sizes near the wavelength of the exposing radiation, the resulting shapes of the printed circuit elements become significantly different from the corresponding pattern on the mask. For example, line widths of circuit elements may vary depending on the proximity of other lines. The inconsistent line widths can then cause circuit components that should be identical to operate at different speeds, thereby creating problems with the overall operation of the integrated circuit. As another example, line ends tend to shorten or “pull back.” The small amount of shortening becomes more significant as the lines themselves are made smaller. Furthermore, pulling back of the line ends can cause connections to be missed or to be weakened and prone to failure.
Accordingly, Optical Proximity Correction (OPC) was developed in the early 1970's as a means of addressing lithography distortions in semiconductor manufacturing. The goal of OPC is to produce smaller features in an IC using a given equipment set by enhancing the “printability” of a wafer pattern. In particular, OPC applies systematic changes to photomask geometries to compensate for nonlinear distortions caused by optical diffraction and resist process effects. For example, these distortions include line width variations dependent on pattern density that affect a device's speed of operation, and line end shortening that can break connections to contacts. Causes include reticle pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. A mask incorporating OPC is thus a system that seeks to negate undesirable distortion effects during pattern transfer.
OPC works by making small changes to the IC layout that anticipate the distortions. To compensate for line end shortening, the line is extended using a hammerhead shape that results in a line in the resist that is much closer to the original intended layout. To compensate for corner rounding, serif shapes are added to (or subtracted from) corners to produce corners in the silicon that are closer to the ideal layout. Determining the optimal type, size, and symmetry (or lack thereof) is very complex and depends on neighboring geometries and process parameters. Moreover, a sophisticated computer program is typically necessary to properly implement OPC.
Thus, as the gap between desired and available lithography resolution continues to widen, even more complex resolution enhancement techniques (RET) and OPC are employed to maintain profitable chip yields. However, the task of verifying whether these complex RET and OPC solutions have achieved optimized (or even adequate) mask patterns is not a trivial endeavor. Model-based verification, also referred to as optical rules checking (ORC), is an approach in which shape checking is implemented on simulated wafer images. Although simulated wafer images of RET and OPC enhanced layout shapes provide excellent qualitative insight into the patterning of certain layout shapes (and in some cases allow the extraction of quantitative information such as localized feature width or space), it is extremely difficult to guarantee that all of the millions of shapes on a given photomask will yield functional circuitry. This is in part due to the challenge of formulating efficient, fail-safe measurements on a vast number of simulated images without drowning the output report with false nuisance errors.
Another contributing factor for making reliable ORC on large designs difficult is the ambiguous nature of the wafer target specifications. Some parameters, such as channel length control, are extremely well specified and can be measured in the simulated image. However, many catastrophic wafer failures occur on complex two-dimensional shapes, often involving inter-level interactions that cannot be easily specified or measured on a simulated wafer image.